From: Ian Campbell Date: Mon, 17 Mar 2014 17:27:40 +0000 (+0000) Subject: xen: arm: make stage 2 page tables walks inner-shareable X-Git-Tag: archive/raspbian/4.8.0-1+rpi1~1^2~5391 X-Git-Url: https://dgit.raspbian.org/%22http://www.example.com/cgi/success//%22http:/www.example.com/cgi/success/?a=commitdiff_plain;h=8200daed053bc7f3dca4ee5b42d9f84934b998d7;p=xen.git xen: arm: make stage 2 page tables walks inner-shareable The comment was previously incorrect and indicated that these mappings were unshared (00) when in reality the register was set for outer-shareable (01). Clarify ORGN0/IRGN0 in the comments while at it. Signed-off-by: Ian Campbell Acked-by: Julien Grall --- diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index e9b3f349c6..6f1408b107 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -378,16 +378,17 @@ void __init arch_init_memory(void) void __cpuinit setup_virt_paging(void) { /* Setup Stage 2 address translation */ - /* SH0=00, ORGN0=IRGN0=01 + /* SH0=11 (Inner-shareable) + * ORGN0=IRGN0=01 (Normal memory, Write-Back Write-Allocate Cacheable) * SL0=01 (Level-1) * ARVv7: T0SZ=(1)1000 = -8 (32-(-8) = 40 bit physical addresses) * ARMv8: T0SZ=01 1000 = 24 (64-24 = 40 bit physical addresses) * PS=010 == 40 bits */ #ifdef CONFIG_ARM_32 - WRITE_SYSREG32(0x80002558, VTCR_EL2); + WRITE_SYSREG32(0x80003558, VTCR_EL2); #else - WRITE_SYSREG32(0x80022558, VTCR_EL2); + WRITE_SYSREG32(0x80023558, VTCR_EL2); #endif isb(); }